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Memory for Plug & Play
I C BUS 3Ports for HDMI Port Serial EEPROM
BU9883FV-W
Description BU9883FV-W is for DDC 3 ports, 2K x 8 bit array 3 BANK EEPROM. Features There are 3 BANKs, 1 BANK compose of 256 word address x 8 bit EEPROM There are 3 DDC interface channels, and each channel can access each BANK independently from other ports. 2K bit X 3 BANK memory bits can be accessed from write port (Port0). Operate voltage (3.0V5.5V) Built in diode for power supply from HDMI ports and system. Automatic erase 8 byte page write mode Low power consumption Active ( 5.0V ) : 1.2mA (Typ.) Standby ( 5.0V ) : 100A(Max.) DATA security Write Protect pin can switch write port Inhibit to WRITE at low VCC Pin package ------ SSOP16pin Endurance : 1,000,000 erase/write cycles Data retention : 40 years Filtered inputs in all SCLSDA for noise suppression Shipment data all address FFh Absolute maximum rating (Ta=25) Parameter Symbol Rating Supply Voltage Vcc -0.36.5 Power Dissipation Pd 400 *1 Storage Temperature Tstg -65 125 Operating Temperature Topr -40 85 Terminal Voltage -0.3Vcc0.3 *1 *1 Degradation is done at 3.0mW/ for operation above 25 *2 The Max value of terminal voltage is not over 6.5V Unit V mW V
2
EEPROM recommended operating condition Parameter Symbol Supply Voltage Vcc Input Voltage VIN
Rating 3.05.5 0 Vcc03
Unit V
Jan. 2009
Memory cell characteristics(Ta=25, Vcc03 = 3.05.5V) Specification Parameter Min. Typ. Max. Write/Erase Cycle Data Retention *1 *1 1,000,000 40
Unit Cycles Years
*1:Not 100 TESTED Input/output capacity (Ta=25, Frequency=5MHz) Parameter SDA pins (SDA0,1,2,3) *1 SCL pins (SCL0,1,2,3) *1 Symbol Cin Cin2 Min. Typ. 7 7 Max. Unit pF pF
*1:Not 100 TESTED EEPROM DC operating characteristics (Unless otherwise specified, Ta=-4085, Vcc03 = 3.05.5V)
Parameter "H" Input Voltage0 "L" Input Voltage0 "H" Input Voltage1 "L" Input Voltage1 "H" Input Voltage2 "L" Input Voltage2 "H" Input Voltage3 "H" Input Voltage3 "L" Output Voltage0 "L" Output Voltage1 "L" Output Voltage2 "L" Output Voltage3 WP "H" Input Voltage WP "L" Input Voltage Input Leakage Current0 Input Leakage Current1 Output Leakage Current0 Symbol VIH0 VIL0 VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOL0 VOL1 VOL2 VOL3 VIH4 VIL4 ILI0 ILI1 ILO0 ICC1 Operating Current ICC2 Standby Current Standby Current Standby Current Standby Current ISB0 ISB1 ISB2 ISB3 Specification Min. Typ. Max. Unit Test condition
0.7xVcc0 -0.3 0.7xVcc1 -0.3 0.7xVcc2 -0.3 0.7xVcc3 -0.3

110
Vcc0+0.5 0.3xVcc0 Vcc1+0.5 0.3xVcc1 Vcc2+0.5 0.3xVcc2 Vcc3+0.5 0.3xVcc3 0.4 0.4 0.4 0.4 Vcc0+0.3 0.3xVcc 1 230 1 2.0 1.0 100 100 100 100
V V V V V V V V V V V V V V A A A mA mA A A A A
3.0Vcc05.5VSCL0, SDA0 3.0Vcc05.5VSCL0, SDA0 3.0Vcc15.5VSCL1, SDA1 3.0Vcc15.5VSCL1, SDA1 3.0Vcc25.5VSCL2, SDA2 3.0Vcc25.5VSCL2, SDA2 3.0Vcc35.5VSCL3, SDA3 3.0Vcc35.5VSCL3, SDA3 IOL=3.0mA , 3.0VVcc05.5VSDA0 IOL=3.0mA , 3.0VVcc15.5VSDA1 IOL=3.0mA , 3.0VVcc25.5VSDA2 IOL=3.0mA , 3.0VVcc35.5VSDA3 3.0Vcc05.5VWPB 3.0Vcc05.5VWPB VIN=05.5VSCL03 WPB=5.5V , Vcc=5.5V VOUT=05.5SDA03 Vcc0=5.5V, fSCL=400kHztWR=5ms Byte Write, Page Write Vcc03=5.5V, fSCL=400kHz Random Read, Current Read, Sequential Read, (each port operation) Vcc0=5.5V, SDA03=SCL03=5.5V, WPB=GND Vcc1=5.5V, SDA03=SCL03=5.5V, WPB=GND Vcc2=5.5V, SDA03=SCL03=5.5V, WPB=GND Vcc3=5.5V, SDA03=SCL03=5.5V, WPB=GND

0.7xVcc0 -0.3 -1 55 -1

This product is not designed for protection against radioactive rays.
2/18
EEPROM AC operating characteristics (Ta=-4085, Vcc03 = 3.05.5V)
Parameter Symbol 3.0Vcc035.5V Min. Typ. Max. Unit Min.
Clock Frequency Data Clock High Period Data Clock Low Period SDA0~3 and SCL0~3 Rise Time SDA0~3 and SCL0~3 Fall Time Start Condition Hold Time Start Condition Setup Time Input Data Hold Time Input Data Setup Time Output Data Delay Time Output Data Hold Time Stop Condition Setup Time Bus Free Time Write Cycle Time Noise Spike Width (SDA0~3 and SCL0~3) WP Hold Time WP Setup Time WP valid time Synchronous data input/output timing
tR SCL tF tHIGH
fSCL tHIGH tLOW *1 *1 tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHD:WP tSU:WP tHIGH:WP
0.6 1.2 0.6 0.6 0 100 0.1 0.1 0.6 1.2 0 0.1 1.0

400 0.3 0.3 0.9 5 0.1
kHz s s s s s s ns ns s s s s ms s ns s s
*1 : Not 100% TESETED
SCL
tHD:STA SDA (IN) tBUF SDA (OUT) tPD tDH tSU:DAT tLOW tHD:DAT
tSU:STA SDA
tHD:STA
tSU:STO
START BIT
STOP BIT
Fig.-1 SYNCHRONOUS DATA TIMING SDA data is latched into the chip at the rising edge of the SCL clock. (This is commoness in all port.) Output date toggles at the falling edge of the SCL clock. (This is commoness in all port.)
Characteristic data (The following values are Typ. ones).
6 6
6
H INPUT VOLTAGE0 : VIH0V
H INPUT VOLTAGE1 : VIH1V
5 4 3 2 1 0 0
5 4 3 2 1 0
H INPUT VOLTAGE2 : VIH2V
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
5 4 3 2 1 0
Ta=-40 Ta=25 Ta=85
SPEC
SPEC
SPEC
1
2 3 4 5 SUPPLY VOLTAGE : Vcc0V
6
0
1
2 3 4 5 SUPPLY VOLTAGE : Vcc0V
6
0
1
2 3 4 5 SUPPLY VOLTAGE : Vcc2V
6
Fig.2'H' Input Voltage0VIH0 (SCL0,SDA0)
6 5 4 3 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc3V 6
Fig.3'H' Input Voltage1VIH1 (SCL1,SDA1)
6 L INPUT VOLTAGE0 : VIL0V 5 4 3 2 1 0 6
Fig.4'H' Input Voltage2VIH2 (SCL2,SDA2)
L INPUT VOLTAGE1 : VIL1V
H INPUT VOLTAGE3 : VIH3V
Ta=-40 Ta=25 Ta=85 SPEC
Ta=-40 Ta=25 Ta=85
5 4 3 2 1 0
Ta=-40 Ta=25 Ta=85
SPEC
SPEC
0
1
2 3 4 5 SUPPLY VOLTAGE : Vcc0V
6
0
1
SUPPLY VOLTAGE : Vcc1V
2
3
4
5
6
Fig.5'H' Input Voltage3VIH3 (SCL3,SDA3)
Fig.6'L' Input Voltage0VIL0 (SCL0,SDA0)
Fig.7'L' Input Voltage1VIL 1 (SCL1,SDA1)
3/18
Characteristic data (The following values are Typ. ones).
6 L INPUT VOLTAGE2 : VIL2V 5 4 3 2 1 0
0 1 2 3 4 5 6
6
1
Ta=-40 Ta=25 Ta=85
L INPUT VOLTAGE3 : VIL3V
5 4 3 2 1 0
0
Ta=-40 Ta=25 Ta=85
L OUTPUT VOLTAGE0 : VOL0V
0.8 0.6 0.4 0.2 0
Ta=-40 Ta=25 Ta=85
SPEC
SPEC
SPEC
1
2
3
4
5
6
0
SUPPLY VOLTAGE : Vcc2V
SUPPLY VOLTAGE : Vcc3V
1 2 3 4 5 L OUTPUT CURRENT : IOLmA
6
Fig.8'L' Input Voltage2VIL 2 (SCL2,SDA2)
1 L OUTPUT VOLTAGE1 : VOL1V
L OUTPUT VOLTAGE2 : VOL2V 1
Fig.9'L' Input Voltage3VIL 3 (SCL3,SDA3)
1
Fig.10 'L' Output Voltage0 VOL0-IOLVcc0=3.0V
0.8 0.6
Ta=-40 Ta=25 Ta=85 SPEC
0.8 0.6
Ta=-40 Ta=25 Ta=85 SPEC
L OUTPUT VOLTAGE3 : VOL3V
0.8 0.6
Ta=-40 Ta=25 Ta=85 SPEC
0.4 0.2 0 0 1 2 3 4 5 L OUTPUT CURRENT : IOLmA 6
0.4 0.2 0 0 1 2 3 4 5 6 L OUTPUT CURRENT : IOLmA
0.4 0.2 0 0 1 2 3 4 5 L OUTPUT CURRENT : IOLmA 6
Fig.11 'L' Output Voltage1 VOL1-IOLV13.0VSDA1
5
WP L INPUT VOLTAGE : VIL4V
WP H INPUT VOLTAGE : VIH4V
Fig.12 'L' Output Voltage2 VOL2-IOLV23.0VSDA2
5
Fig.13 'L' Outnput Voltage3 VOL3-IOLV33.0VSDA3
1.2
4 3 2 1 0
0
Ta=-40 Ta=25 Ta=85
SPEC
4 3
Ta=-40 Ta=25 Ta=85
INPUT LEAK CURRENT0 : ILI0uA
1 0.8 0.6 0.4 0.2 0 0
Ta=-40 Ta=25 Ta=85
SPEC
2 1 0
SPEC
1
2
3
4
5
6
7
8
0
1
2
L OUTPUT CURRENT : Vcc0V
3 4 5 6 7 SUPPLYVOLTAGE : Vcc0V
8
Fig.14WP 'H' Input Voltage VIH4
Fig.15WP 'L'Input Voltage VIL4
1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc03V Fig.16Input Leak Cu0 ILI0(SCL03)
250 INPUT LEAK CURRENT0 : ILI1uA 200 150 100 50 0 0 1 2 3 4 5 SUPPLY VOLTAGE : VccV 6
2.5 OUTPUT LEAK CURRENT1 : ILOuA
2500 CURRENT CONSUMPTION AT WRITTING : Icc1mA
Ta=-40 Ta=25 Ta=85
2
Ta=-40 Ta=25 Ta=85 SPEC
2000 1500 1000 500 0
Ta=-40 Ta=25 Ta=85
SPEC
1.5 1
SPEC
0.5 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : VccV
SCL=400Hz WR=5ms
0
1 2 3 4 5 SUPPLY VOLTAGE : Vcc0V
6
Fig.17Input Leak Current1 ILI1WPB
Fig.18 OUTPUT LEAK CURRENT ILO SDA03
STANDBY CURRENT : ISB1[uA]
300
Fig.19 Current Consumption at Reading Icc1
300
1500 CURRENT CONSUMPTION AT READING2 : Icc2mA
1000
Ta=-40 Ta=25 Ta=85
STANDBY CURRENT : ISB0uA
250 200 150 100 50 0
SPEC
Ta=-40 Ta=25 Ta=85
250 200 150
Ta=-40 Ta=25 Ta=85
SPEC
100 50 0
500
SCL=400Hz Each port operation
SPEC
0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc03[V] 6
0
1
2 3 4 5 SUPPLY VOLTAGE : Vcc0[V]
6
0
1 2 3 4 5 SUPPLY VOLTAGE : Vcc1V
6
Fig.20Current Consumption at Reading Icc2
Fig.21Standby Current ISB0
Fig.22 Standby Current ISB1
4/18
Characteristic data (The following values are Typ. ones).
300 STANDBY CURRENT : ISB2[uA]
300 STANDBY CURRENT : ISB3[uA]
CLOCK FREQUENCY : SCLHz
1000
250 200 150 100 50 0 0
Ta=-40 Ta=25 Ta=85 SPEC
250 200 150 100 50 0
0
Ta=-40 Ta=25 Ta=85
800
Ta=-40 Ta=25 Ta=85 SPEC
600
SPEC
400
200
1
2 3 4 5 SUPPLY VOLTAGE : Vcc2[V]
6
0 1 2 3 4 SUPPLY VOLTAGE : Vcc3[V] 5 6 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
Fig.23 Standby Current2ISB2
Fig.24 Standby CurrentISB3
Fig.25Clock Frequency fSCL
DATA CLOCK LOW PERIOD : tLOWus
DATA CLOCK HIGH PERIOD : tHIGHus
800 700 600 500 400 300 200 100 0 0 1 2 3 4 SUPPLY VOLTAGE : Vcc[V] 5 6
1400 1200 1000 800 600 400 200 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
START CONDITION HOLD TIME : tHD:STAus
800
SPEC
600
SPEC
Ta=-40 Ta=25 Ta=85
SPEC
400
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
200
0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
Fig.26Data Clock H PeriodtHIGH
Fig.27Data Clock Low PeriodtLOW
Fig.28 S Condition Hold TimeHD:STA
INPUT DATA HOLD TIME : tHD:DATns
20 0 -20 -40 -60 -80 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
DATA SETUP TIME : tSU:DATns
800 START CONDITION SETUP TIME : tSU:STAus
120
SPEC
600
SPEC
100 80 60 40 20 0 0 1 2 3 4 5 SUPPLY VOLATGE : Vcc[V] 6
SPEC
400
Ta=-40 Ta=25 Ta=85
200
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
Fig.29 Start Condition Setup Time tSU:STA
OUTPUT DATA DELAY TIME : tPDus 1000 STOP CONDITION SETUP TIME : tSU :STOus 800 600 400 200 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6 800
Fig.30Input Data Hold TimetHDDAT
Fig.31Input Data Setup TimeSU:DAT
6
Ta=-40 Ta=25 Ta=85
SPEC
600 400 200 0 -200 0
Ta=-40 Ta=25 Ta=85
SPEC
Write Cycle Time TIME : tWRms
5 4 3 2 1 0 0
Ta=-40 Ta=25 Ta=85
SPEC
1
2 3 4 5 SUPPLYVOLTAGE : Vcc[V]
6
1
2 3 4 5 SUPPLYVOLTAGE : Vcc[V]
6
Fig.32 Output Data Delay TimePD
400 NOISE SPIKE WIDTH (SDA03 and SCL03) : tIus WP SET UPTIME : tSU : WPus 200
Fig.33 Stop Condition Setup Time tSUSTO
Fig.34 Write Cycle Time tWR
300
Ta=-40 Ta=25 Ta=85
100 0 -100 -200 -300
0
Ta=-40 Ta=25 Ta=85
SPEC
200
100
SPEC
0 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc[V] 6
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc[V]
Fig.35 Noise Spike Width tI (SDA03 and SCL03)
Fig.36 WP Setup Time tSU:WP
5/18
Pin configuration
Vcc1 SCL1 SDA1 WPB VCC OUT SDA0 SCL0 Vcc0
1 2 3 4 5 6 7 8
16 15 14
Vcc2 SCL2 SDA2 N.C GND SDA3 SCL3 Vcc3
BU9883FV-W
13 12 11 10 9
Fig.37 Pin configuration
PIN NAME PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN NAME Vcc1 SCL1 SDA1 WPB VCC OUT SDA0 SCL0 Vcc0 Vcc3 SCL3 SDA3 GND N.C SDA2 SCL2 Vcc2 I/O Input Input / output Input Input / output Input Input Input / output Input / output Input Power Supply Serial clock input Slave and word address, Serial data input serial data output Write protect terminal1 : Write enable, 0 : Write disable Terminal of diode. Connect Bypass capacitor. Slave and word address, Serial data input serial data output Serial clock input Power Supply Power Supply Serial clock input Slave and word address, Serial data input serial data output Reference voltage of all input / output Non connect terminal. Don't connect each other. Slave and word address, Serial data input serial data output Serial clock input Power Supply FUNCTIONS
6/18
BLOCK DIAGRAM
Vcc1 Vcc2 Vcc3
Voltage Detect Logic
Vcc0
LDO Low Voltage Logic
VCC OUT
WPB Port SCL1 SDA1
EN I/O
LEVEL Shifter
CONTROL
RD
BANK0
(2Kbit EEPROM)
WR RD Port 0
(PORT1)
Port 2 SCL2 SDA2
EN
I/O (PORT2)
LEVEL Shifter
RD CONTROL
BANK1
(2Kbit EEPROM)
WR
CONTROL
LEVEL Shifter
I/O (PORT0)
EN SCL0 SDA0
SCL0 SDA0
RD
Port SCL3 SDA3
EN I/O (PORT3)
LEVEL Shifter
CONTROL RD
BANK2
(2Kbit EEPROM)
WR RD
Fig.38 BLOCK DIAGRAM
HDMI Sink 0.1uF PWR_HDMI1 DDC_SCL1 DDC_SDA1 0.1uF PWR_HDMI2 DDC_SCL2 DDC_SDA2 0.1uF SCL0 PWR_HDMI3 DDC_SCL3 DDC_SDA3
47K 47K 47K 47K 47K 47K
Vcc1 SCL1 SDA1
PWR_SYS Vcc0 0.1uF WPB Controller WPB_OUT I2C_SCL 0.1uF I2C_SDA
ROHM Vcc OUT
Vcc2 BU9883FV-W SCL2 SDA2
Vcc3 SDA0 SCL3 SDA3 GND HDMI Receiver
SDA3 SCL3 SDA2 SCL2 SDA1 SCL1 SCL_SINK
HDMI Switch
SDA_SINK
DDC_SCL
DDC_SDA
Fig.39 Application circuit
7/18
WRITE CYCLE TIMING
SCL0
SDA0
D0 WRITE DATA(n)
ACK
tWR
STOP CONDITION START CONDITION
Fig.40 WRITE CYCLE TIMING
WRITE OPERATION BU9883FV-W has 2K bit EEPROM in each port, there are three BANKs, 6K bit EEPROM in this device. Each BANK EEPROM can be written through PORT0. There is no write operation through PORT1,2,3. When this device is accessed throgh PORT0, WPB terminal must be set to "HIGH". Table1 Access port and write enable BANK Port0 Port1 Port2 Port3 BANK13 No write operation No write operation No write operation
READ OPERATION Each BANK EEPROM can be read through each port. The relation ship of access port and access BANK is describe Table2. Table 1 Table 2 Port0 BANK13 Port0 BANK13 Port1 No write operation Port1 BANK1 Port2 No write operation Port2 BANK2 Port3 No write operation Port3 BANK3 When EEPROM access through PORT0, P1, P0 bits in slave address appoint access BANK. Table 3 P1 P0 P1,P0 bit and access BANK 0 0 No bank selected 0 1 BANK1 1 0 BANK2 1 1 BANK3 Note) When P1=0, P0=0 : this device doesn't return Acknowlege. During PORT0 access, WPB terminal must be set to "HIGH", then PORT13 accesses will be cancelled. In accessing from PORT13, set WPB termianl to "LOW" DEVICE OPERATION START CONDITION All commands are proceeded by the start condition, which is a HIGH to LOW transition of SDA03 when SCL03 is HIGH. This device continuously monitors the SDA03 and SCL03 lines for the start condition and will not respond to any command until this condition has been met. STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA0 3when SCL03 is HIGH. The stop condition initiates internal write cycle to write the data into memory array after write sequence. The stop condition is also used to place the device into the standby power mode after read sequence. A stop condition can only be issued after the transmitting device has released the bus. NOTICE ON WRITE COMMAND In Write command, after transmit write data, if there are no stop condition, EEPROM data don't change.
8/18
DEVICE ADDRESSING Following a START condition, the master output the device address of the slave to be accessed. The most significant four bits of the slave address are the "device type indentifier," for this device, this is fixed as "1010." The next three bit specify a particular device. For PORT0 access, that are set "0", "P1", "P0", for PORT 13 access, that must be set "000". The last bit of the stream determines the operation to be performed. When set to "1" a read operation is selected ; when set to "0," a write operation is selected. R/W set to "0" WRITE R/W set to "1" READ
ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers.The master or the slave will release the bus after transmitting eight bits.During the ninth clock cycle, the receiver will pull the SDA line LOW to Acknowledgethat the eight bits of data has been received. This device will respond with an Acknowledge after recognition of a START condition and its slave address.If both the device and a write operation have been selected, this device will respond with an Acknowledge, after the receipt of each subsequent 8-bit word. In the READ mode, this device will transmit eight bit of data, release the SDA line, and monitor the line for an Acknowledge. If an Acknowledge is detected, and no STOP condition is generated by the master, this device will continue to transmit the data. If an Acknowledge is not detected, this device will terminate further data transmissions and await a STOP condition before returning to the standby mode. This device dosen't return Acknouwedge in internal write cycle.
START CONDITION (START BIT)
SCL
From-COM
1
8
9
SDA
-COM OUTPUT DATA)
SDA
IC OUTPUT DATA
Acknowledge Signal (ACK Signal)
Fig.41 ACKNOWLEDGE RESPONSE FROM RECEIVER PORT0 access commands For PORT0 access, WPB terminal must be set to "HIGH".
S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) DATA(n) S T O P
101
0
0
P1 P0
WA7
WA0
D7
D0 A C K
R / W WPB
A C K
Fig.42 BYTE WRITE CYCLE TIMING (PORT0) This write commands operate EEPROM write sequence at address which is appointed by P1, P0. When the master generates a STOP condition, this device begins the internal write cycle to the nonvolatile array.
9/18
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
1st WORD ADDRESS(n)
DATA(n)
DATA(n+7)
S T O P
101
0
0
P1 P0
WA7
WA0
D7 A C K
D0 A C K
D0 A C K
R / W WPB
A C K
Fig.43 PAGE WRITE CYCLE TIMING (PORT0) This device is capable of eight byte page write operation. After the receipt of each word, the three low order address bits are internally incremented by one. The most significant address bits (WA7WA3) remain constant, if the master transmits more than 8 words. The relationship of P1, P0 inputs and access BANK is described as follows. P1 0 0 1 1 P0 0 1 0 1 BANK No opearation BANK1 BANK2 BANK3
Don't set P1, P0=0, 0. If P1, P0 are set to 0, there is no target bank, so this device doesn't return cknowlege. WPB terminal must be set to "HIGH" during Byte Write cycle, and Page Write cycle, and internal Write cycles. If WPB is set to "LOW" in above condition, programing doesn't work, and during internal Write cycle, WPB terminal set to "LOW", this device terminate programing, and the data in programing address is not stored correctly.
S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) S T A R T SLAVE ADDRESS R E A D DATA(n) S T O P
1
010
0
P1 P0
WA7
WA0
1 A C K
010
0
P1 P0
D7 RA /C WK
D0 A C K
R / W WPB
A C K
Fig.44 RANDOM READ CYCLE TIMINGPORT0 Random read operation allows the master to access any memory location which is appointed by P1, P0 bit. This operation involves a two-step process. First, the master issue a write command which includes the start condition and the slave address field (with R/W set to "0") followed by the address of the word be read. This procedure sets the internal address counter of this device to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by the slave address field with R/W the set to "1." This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. If the master does not acknowledge the transmission but does generate the stop condition, at this point this device discontinues transmission.
S T A R T SDA LINE 1 0 R E A D S T O P
SLAVE ADDRESS
DATA
1
0
0 P1 P0 D7 RA /C WK D0 A C K
WPB
Fig.45 CURRENT READ CYCLE TIMINGPORT0 When the command just before Current Read cycle is Random Read cycle or Current Read cycle (each including Sequential Read cycle), data of incremented last read address (n)-th address, i.e.n, data of the (n+1)-th address is output. When the command just before Current Read cycle is Byte Write or Page write, data of latest write address is output.
10/18
Current Read operation allows the master to access data word stored in internal address counter which is appointed by P1, P0 bit. This operation involves a two-step process. This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. If the master does not acknowledge the transmission but does generate the stop condition, at this point this device discontinues transmission. noteIf the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output next address data, and master can't send stop condition, so master can't discontinues transmission. To stop read command, the master must send no Acknowledge at after D0 output, and issue stop condition.
S T A R T SDA LIN R E A D
D7
SLAVE ADDRESS 1 0 1 0 0 P1 P0
DATA(n)
D0 D7
DATA(n+x
D0
S T O P
WPB
Fig.46 SEQUENTIAL READ CYCLE TIMING PORT0
During the sequential read operation, the internal address counter of this device automatically increments with each acknowledge received ensuring the data from address will be followed with the data from n+1. For read operations, all bits of the address counter are incremented allowing the entire array to be read during a single operation. When the counter reaches the top of the array, it will "roll over" to the bottom of the array of BANK and continue to transmit the data. The sequential read operation can be performed with both current read and random read. PORT1,2,3 access commands
S T A R T SDA LINE W R I T E S T A R T R E A D S T O P
SLAVE ADDRESS
1st WORD ADDRESS(n)
SLAVE ADDRESS
DATA(n)
101
0
00
0 R / W A C K
WA7
WA0
10 A C K
10
00
0 RA /C WK
D7
D0 A C K
WPB
Fig.47 RANDOM READ CYCLE TIMINGPORT13 Random read operation allows the master to access any memory location of the BANK which is appointed by P1, P0. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with R/W set to "0") followed by the address of the word be read. This procedure sets the internal address counter of this device to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by the slave address field with R/W the set to "1." This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. If the master does not acknowledge the transmission but does generate the stop condition, at this point this device discontinues transmission.
S T A R T SDA LINE
SLAVE ADDRESS
R E A D
DATA
S T O P
1
0
10
0
00 R / W A C K
D7
D0 A C K
WPB
Fig.48 CURRENT READ CYCLE TIMINGPORT13
11/18
When the command just before Current Read cycle is Random Read cycle or Current Read cycle (each including Sequential Read cycle), data of incremented last read address (n)-th address, i.e.n, data of the (n+1)-th address is output. When the command just before Current Read cycle is Byte Write or Page write, data of latest write address is output. Random read operation allows the master to access any memory location. The BANK which is appointed by P1, P0. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with R/W set to "0") followed by the address of the word be read. This procedure sets the internal address counter of this device to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by the slave address field with R/W the set to "1." This device will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. If the master does not acknowledge the transmission but does generate the stop condition, at this point this device discontinues transmission. noteIf the master send Acknowredge at after D0 output, Sequential Read is selected, and this device output next address data, and master can't send stop condition, so master can't discontinues transmission. To stop read command, the master must send no Acknowledge at after D0 output, and issue stop condition.
S T A R T SDA LINE
SLAVE ADDRESS
R E A D
DATA(n)
DATA(n+x)
S T O P
1010
0
00 1 R / W A C K
D7
D0 A C K A C K
D7
D0 A C K
WPB
Fig.49 SEQUENTIAL READ CYCLE TIMING PORT13 During the sequential read operation, the internal address counter of this device automatically increments with each acknowledge received ensuring the data from address n will be followed with the data from n+1. For read operations, all bits of the address counter are incremented allowing the entire array to be read during a single operation. When the counter reaches the top of the array, it will "roll over to the bottom of the array and continue to transmit the data. The sequential read operation can be performed with both current read and random read. Access Control of PORT0,1,2,3 WPB terminal controls access enable of each PORT, as follows. WPB terminal inputs PORT 0 1 PORT0 not accessible Read/Write PORT1 Read not accessible PORT2 Read not accessible PORT3 Read not accessible Table4 WPB terminal and port accesibility When WPB terminal is "HIGH", PORT0 only can access this device. In this case, when commands from PORT1, 2, 3 are inputted, these port don't return acknowledge. When WPB terminal is "LOW", PORT0 access is not valid, but PORT1, 2, 3 can access this device this device. Commands from PORT1, 2, 3 is performs independently other port.
12/18
Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.50(a), Fig.50(b), and Fig.50 (c).) In dummy clock input area, release the SDA03 bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices.
Dummy clockx14 Startx2
SCL03 SDA03
1
2
13
14
Normal command Normal command
Fig.50-(a) The case of dummy clock +START+START+ command input
Start Dummy clockx9 Start
SCL03 SDA03
1
2
8
9
Normal command Normal command
Fig.50-(b) The case of START +9 dummy clocks +START+ command input
Startx9
SCL03 SDA03
1
2
3
7
8
9
Normal command Normal command
Fig.50-(c) STARTx9+ command input
Start command from START input.
Acknowledge polling During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data output and so forth.
During internal write, ACK = HIGH is sent back. S T O P S T Slave A R address T A C K H S T Slave A R address T A C K H
First write command
S T A R T
Write command
tWR Second write command
S T Slave A R address T A C K H S T Slave A R address T A C Word K address L A C K L A C K L S T O P
...
Data
tWR
After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession.
Fig.51 Case to continuously write by acknowledge polling
13/18
Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 52.) However, in ACK output area and during data read, SDA03 bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL03
SDA03
1
0
1
0 Start condition Stop condition
Fig.52 Case of cancel by start, stop condition during slave address input
I/O peripheral circuit Pull up resistance of SDA03 terminal SDA03 is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL03-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. The following Vcc, SDA, RPU and IL correspond to them of each port. (1)SDA03 rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA03 should be tR or below. And AC timing should be satisfied even when SDA03 rise time is late. (2)The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA03 bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc. Vcc - ILRPU 0.2Vcc VIH RPU 0.8VccVIH IL Microcontroller
RPU BU9883FV-W
A
SDA terminal
Ex. ) When VCC =3V, IL=10A, VIH=0.7 VCC, from (2) RPU 0.8x30.7x3 10x10
-6
IL
CBUS CBUS
IL
capacity
Bus line
300 [k] Minimum value of RPU (1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. VCCVOL RPU IOL RPU VCVOL IOL Fig.53 I/O circuit diagram
The minimum value of RPU is determined by the following factors. The following Vcc, VOL, IOL, and RPU correspond to them of each port.
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL0.1 VCC Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc from (1) RPU And VOL = 0.4 [V] VIL = 0.3x3 = 0.9 [V] Pull up resistance of SCL03 terminal When SCL03 control is made at CMOS output port, there is no need, but in the case there is timing where SCL03 becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. Therefore, the condition (2) is satisfied. 30.4 3x10 867 []
-3
14/18
Cautions on microcontroller connection Rs In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used. The following SCL SDA RPU and RS correspond to them of each port.
ACK
RPU
SCL RS SDA
'H' output of microcontroller 'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM.
Fig.54 I/O circuit diagram
Fig.55 Input / output collision timing
Maximum value of Rs The maximum value of Rs is determined by the following relations. The following Vcc, VOL, RS, RPU, IOL, and SDA correspond to them
of each port.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2)The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC RPU A RS IOL
Bus line capacity CBUS
(VCCVOL)xRS RPU+RS
VOL
+ VOL+0.1VCCVIL
RS
VILVOL0.1VCC 1.1VCCVIL
x
RPU
ExampleWhen VCC=3V,VIL=0.3VCC,VOL=0.4V,RPU=20k,
EEPROM
VIL
Microcontroller
from(2),
RS
0.3x30.40.1x3 x 1.1x30.3x3
20x10
3
Fig.56 I/O circuit diagram
1.67k
Minimum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below. The following Vcc, RPU, RS, and I correspond to them of each port.
VCC RS
'L' output
I VCC I
RPU RS
RS
Over current 'H' output
ExampleWhen VCC=3V, I=10mA RS 3 -3 10x10
Microcontroller
EEPROM
Fig.57 I/O circuit diagram 15/18
300
I2C BUS input / output circuit
Input (SCL03)
Fig.58 Input pin circuit diagram Input / output (SDA03)
Fig.59 Input / output pin circuit diagram
Input (WPB)
Fig.60 Input pin circuit diagram
16/18
Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following conditions at power on. 1. Set SDA03 = 'H' and SCL03 ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
VCC tR
Recommended conditions of tR, tOFF,Vbot
tR
tOFF Vbot
tOFF
Vbot
10ms or below 10ms or longer 0.3V or below 100ms or below 10ms or longer 0.2V or below
0
Fig.60 Rise waveform diagram 3. Set SDA03 and SCL03 so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition 1 cannot be observed. When SDA03 becomes 'L' at power on. Control SCL03 and SDA03 as shown below, to make SCL03 and SDA03, 'H' and 'H'.
VCC SCL
tLOW
SDA
After Vcc becomes stable After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Fig.61 When SCL03= 'H' and SDA03= 'L' Fig.62 When SCL03='L' and SDA03='L' b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P11). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b). Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC VccOUT and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board VccOUT and GND. Cautions on use (1)Described numeric values and data are design representative values, and the values are not guaranteed. (2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3)Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4)GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5)Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6)Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. 17/18
Ordering part number
B
U
9
Part No.
8
8
3
F
V
-
W
E
2
Part No.
Package FV: SSOP-B16
W: Double Cell Packaging and forming specification E2: Embossed tape and reel
SSOP-B16
Tape Quantity
5.0 0.2
1.15 0.1 6.4 0.3 0.1 4.4 0.2
16 9
Embossed carrier tape 2500pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
1
8
0.15 0.1
0.1 0.65 0.22 0.1
0.3Min.
Direction of feed
1234
Reel
1234
1234
1pin
1234
1234
1234
Direction of feed
1234
1234
Unit:mm)
When you order , please order in times the amount of package quantity.
1st 2009, January
Catalog No. 09002EAT01 '09.1 ROHM (c)
Published by LSI Business Promotion Group
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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